The present invention relates to an interrupt control circuit, and more particularly to an interrupt control circuit operative to produce interrupt vector information from interrupt vector generators configured as a memory matrix array in response to interrupt requests. Specifically, the present invention is concerned with an interrupt control circuit wherein each interrupt vector generator has a self-addressing function to provide access to the self-addressed interrupt vector generator to thereby output interrupt vector information via a single output buffer.
First, a conventional interrupt control circuit will be described with reference to FIG. 1. This circuit includes input terminals 1, 2 and 3 receiving interrupt request signals, latch circuits 4, 5 and 6 connected to the input terminals 1, 2 and 3, respectively, an output terminal 7 for transmitting an interrupt request signal to a CPU (not shown), which is connected to respective outputs of the latch circuits 4, 5 and 6 through an OR gate 8, and an input terminal 9 for receiving an interrupt acknowledge signal from the CPU. The interrupt control circuit further includes AND gates 10, 11 and 12 for forming logical products outputs from the latch circuits 4, 5 and 6 and the interruption acknowledge signal from the input terminal 9, respectively, interruption vector generators 13, 14 and 15 each having a plural bit configuration, output buffers 16, 17 and 18 each having a plural bit configuration and outputting respective output signals from the interrupt vector generators 13, 14 and 15 depending upon the output states of the AND gates 10, 11 and 12, and a data bus 19 coupled in parallel with the output buffers 16, 17 and 18.
For instance, when an interrupt request signal is inputted to the input terminal 1, the latch circuit 4 becomes operative to latch the interrupt request signal. The output signal of the latch circuit 4 is fed to one input terminal of the AND gate 10 and is also fed to the output terminal 7 through the OR gate 8 as an interrupt request signal to the CPU. When the CPU accepts this interrupt signal, it outputs an interrupt acknowledge signal to the input terminal 9. As a result, the output buffer 16 is enabled by the interrupt acknowledge signal. Thus, an output signal (interrupt vector information) from the interrupt vector generator 13 is outputted to the data bus 19 via the output buffer 16. Further, in the case where an interrupt request signal is fed to the input terminal 2 or 3, a similar interrupt operation is carried out. Namely, interrupt vector information from the interrupt vector generator 14 and 15 is outputted to the data bus 19 via the output buffer 17 or 18.
In the above-mentioned conventional circuit for controlling a plurality of interrupts, output buffers having a plural bit configuration in the same number as that of the received interrupt are connected to the data bus 19. Accordingly, a large amount of traffic due to the large number of output buffers is placed on the data bus, with the result that the average signal transmission speed is lowered.
Further, from a mask layout point of view, it is difficult to accommodate a large number of output buffers having a large area.